Automatic test program generation for verifying microprocessors

As simulation is still the most widely used reviews the related work addressing microprocessor architecture level test program generation.

Section 3 describes form of microprocessor Verification: millions of cycles are our method in details. Section 4 gives the implementation of spent during simulation using a combination of random and our MA'TG tool and the experimental results of our prototype directed test cases in traditional design flow. Certain heuristics and design abstractions are used to generate directed random system on DLX processor verification. Section 5 gives test cases. However, it is very time-consuming to write all test concluding remarks.

This brings about the necessity of developing an automatic program generator APG to speed up Related Work the verification work. Therefore, our objective is designing an APG to shorten the verification cycle.

Recently, ADL Our method is a kind of model-based test generation method. With a unique ADL specification, the methodology system techniques to develop a test program generator for can produce functional simulator, conduct design verification, design verification of hardware processors. The test program and explorh design space [I]. However, it was aimed toward verifying program generation methodology.

It is not easy to generate a specific In this paper, we proposed the specification driven and instruction sequence to verify some functional blocks with constraints solving based test program generation method for MBTG. For example, it takes 3 model-based test generator [ 2 ].

In our method, the months to build model for a DSP [4]. First, we automatically concepts like symbolic execution, constraint solving, and biasing techniques to generate tests. However, it provides a very detailed way for the user to control the test pattern. Aharan et al. China under grant No. In our approach, we use the user constraints generated EXE program, it will generate the test program that meets user needs. Besides composing the constraints in user constraints file to C t t codes, the constraints compiler will also zyxwvutsrqpo descriptions to achieve the same purpose.

Bin et al. In contrast, our constraint-solving system for the problem is the B. Because our method is for test pattern generation, and can generate random and specific microprocessor architecture verification, we concern more of test program.

However, in their method, they cannot guarantee the instruction set architecture than of the structure information. In our method, we instruction descriptions, including the opcode, operands, can certainly generate specific test programs for user instruction format and the operation semantic of each constraints.

Prabhat Mishra et a1 [9] also present a instruction, the conditions when each instruction will cause zyxwvutsr specification driven test generation method. However, they can exception are also described. Reader can refer to [ I ] for zyxwv only deal with the pipeline of the microprocessor, while our detailed description. In future work, we will define our own method can deal with all the microprocessor architecture ADL.

Instruction Template Library Each instruction has a corresponding C t t class in the library. Each instruction class contains the syntax information of the instruction, such as instruction opcode, operands, and format. It also contains the semantic model of the instruction, such as operation semantic.

Besides some regular class methods, such as printing the proper instruction format, there are also some methods in the class to add some 1 6 Execute user independent constraints and some complex constraints. Also, in order to generate valid memory access instruction, Test Program memory access instruction classes contain the constraints methods that deal with address alignment.

All these constraints zyxwvu Fig. Test Program Generation Methodology methods encapsulate in instruction classes have two advantages.

First, it will guarantee generation of valid Fig, 1 shows our specification driven and constraints solving instruction. Second, it will ease the constraints writing task. In our methodology For example, to let the DLX ADD instruction produce scenario, the designer first specifies the microprocessor overflow exception, user only need to attach an annotation to architecture in an ADL.

Our methodology is independent of the constraints specification. The portal can access those files and use them to remember the user's data, such as their chosen settings screen view, interface language, etc. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal.

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Authors: Advanced Search Include Citations. Venue: ACM Trans. Design Automation of Electric Systems Citations: 2 - 0 self. Abstract A novel Backus-Naur-form- BNF- based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented in this paper. Keyphrases test program compatible microprocessor verification bnfbased automatic test program generator coverage tool design issue design method user menu-driven file high coverage complex one experimental evaluation flex-ible program size data cache testable small number specific module controllable data dependency x86 ar-chitecture top-down recursive descent advanced microprocessor automatic program gener-ator illegal state novel backus-naur-form bnf production rule random test program infinite loop compiler design processor architecture generated test program.